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* othe r brand s an d name s ar e th e propert y o f thei r respectiv e owners. informatio n i n thi s documen t i s provide d i n connectio n wit h inte l products . inte l assume s n o liabilit y whatsoever , includin g infringemen t o f an y paten t or copyright , fo r sal e an d us e o f inte l product s excep t a s provide d i n intel' s term s an d condition s o f sal e fo r suc h products . inte l retain s th e righ t t o make change s t o thes e specification s a t an y time , withou t notice . microcompute r product s ma y hav e mino r variation s t o thi s specificatio n know n a s errata. july 2004 copyright ? intel corporation, 2004 order number: 272335-004 87c51 /80c51bh/80c31bh chmo s single-chip 8-bit microcontroller commercial/express 87c51 /80c51bh/80c51bhp/80c31bh *se e table 1 for proliferation options high performance chmos eprom 2 4 mh z operation improved quick-pulse programming algorithm 3-level program memory lock boolean processor 128-byte data ram 3 2 programmable i/o lines two 16-bit timer/counters extended temperature range ( - 40 c to + 85 c) 5 interrupt sources programmable serial port ttl- and cmos-compatible logic levels 64 k external program memory space 64 k external data memory space onc e mode facilitates system testing power control modes ? idle ? power down memor y organization progra m memory : u p t o 4 kbyte s o f th e progra m memor y ca n resid e on-chi p (excep t 80c31bh) . in additio n th e devic e ca n addres s u p t o 64 k o f progra m memor y externa l t o th e chip. dat a memory : thi s microcontrolle r ha s a 12 8 x 8 on-chi p ram . i n additio n i t ca n addres s u p t o 6 4 kbyte s of externa l dat a memory. th e inte l 87c51 /80c51bh /80c31b h i s a single-chi p control-oriente d microcontrolle r whic h i s fabricate d on intel' s reliabl e chmo s iii- e technology . bein g a membe r o f th e mcs ? 5 1 controlle r family , the 87c51/80c51bh/80c31b h use s th e sam e powerfu l instructio n set , ha s th e sam e architecture , an d i s pin-for- pi n compatibl e wit h th e existin g mc s 5 1 controlle r famil y o f products. th e 80c51bh p i s identica l t o th e 80c51bh . whe n orderin g th e 80c51bhp , customer s mus t submi t th e 64 byt e encryptio n tabl e togethe r wit h th e ro m code . loc k bi t 1 wil l b e se t t o enabl e th e interna l ro m code protectio n an d a t th e sam e tim e allow s cod e verification. th e extremel y lo w operatin g power , alon g wit h th e tw o reduce d powe r modes , idl e an d powe r down , make thi s par t ver y suitabl e fo r lo w powe r applications . th e idl e mod e freeze s th e cp u whil e allowin g th e ram, timer/counters , seria l por t an d interrup t syste m t o continu e functioning . th e powe r dow n mod e save s the ra m content s bu t freeze s th e oscillator , causin g al l othe r chi p function s t o b e inoperative. fo r th e remainde r o f thi s document , th e 87c51 , 80c51bh , an d 80c31b h wil l b e referre d t o a s th e 87c51/bh, unles s informatio n applie s t o a specifi c device.
87c51/80c51bh/80c31bh table 1. proliferation options * standard -1 -2 -24 80c31bh x x x x 80c51bh x x x x 80c51bhp x x x x 87c51 x x x x notes : * 3.5 mhz to 12 mhz; v cc e 5v g 20% -1 3.5 mhz to 16 mhz; v cc e 5v g 20% -2 0.5 mhz to 12 mhz; v cc e 5v g 20% -24 3.5 mhz to 24 mhz; v cc e 5v g 20% 272335 1 figure 1. 87c51/bh block diagram 2
87c51/80c51bh/80c31bh proces s information th e 87c51-b h i s manufacture d o n th e chmo s iii-e process . additiona l proces s an d reliabilit y informa- tio n i s available in the intel ? quality system handbook . 87c51-b h di p (otp) 40-pi n cerdip ( e p r om) 44-pi n plc c (otp) 44-pi n qf p (otp) 272335 C 2 dip 272335 C 3 plcc 272335 C 4 *d o no t connec t reserve d pins. qfp figure 2. pin connections 3 40-pi n plastic
87c51/80c51bh/80c31bh pin description v cc : supply voltage during normal, idle and power down operations. v ss : circuit ground. port 0 : port 0 is an 8-bit open drain bidirectional i/o port. as an output port each pin can sink several ls ttl inputs. port 0 pins that have 1s written to them float, and in that state can be used as high-imped- ance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external memory. in this application it uses strong internal pullups when emit- ting 1s. port 0 also receives the code bytes during eprom programming, and outputs the code bytes during program verification. external pullups are required during program verification. port 1 : port 1 is an 8-bit bidirectional i/o port with internal pullups. the port 1 output buffers can drive ls ttl inputs. port 1 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current (i il , on the data sheet) because of the internal pull- ups. port 1 also receives the low-order address bytes during eprom programming and program verifica- tion. port 2 : port 2 is an 8-bit bidirectional i/o port with internal pullups. port 2 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current (i il , on the data sheet) because of the internal pull- ups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit address (movx dptr). in this application it uses strong internal pullups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx ri), port 2 emits the con- tents of the p2 special function register. port 2 also receives some control signals and the high-order address bits during eprom programming and program verification. port 3: port 3 is an 8-bit bidirectional i/o port with internal pullups. the port 3 output buffers can drive ls ttl inputs. port 3 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current (i il , on the data sheet) because of the pullups. port 3 also serves the functions of various special features of the mcs-51 family, as listed below: pin name alternate function p3.0 rxd serial input line p3.1 txd serial output line p3.2 int0 external interrupt 0 p3.3 int1 external interrupt 1 p3.4 t0 timer 0 external input p3.5 t1 timer 1 external input p3.6 wr external data memory write strobe p3.7 rd external data memory read strobe port 3 also receives some control signals for eprom programming and program verification. rst: reset input. a high on this pin for two machine cycles while the oscillator is running resets the de- vice. the port pins will be driven to their reset condi- tion when a minimum v ih1 voltage is applied wheth- er the oscillator is running or not. an internal pull- down resistor permits a power-on reset with only a capacitor connected to v cc . ale/prog : address latch enable output signal for latching the low byte of the address during accesses to external memory. this pin is also the program pulse input (prog ) during eprom programming for the 87c51. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with this bit set, the pin is weakly pulled high. however, the ale disable fea- ture will be suspended during a movx or movc in- struction, idle mode, power down mode and ice mode. the ale disable feature will be terminated by reset. when the ale disable feature is suspended or terminated, the ale pin will no longer be pulled up weakly. setting the ale-disable bit has no effect if the microcontroller is in external execution mode. 4
87c51/80c51bh/80c31bh in normal operation ale is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory. psen : program store enable is the read strobe to external program memory. when the 87c51/bh is executing from internal program memory, psen is inactive (high). when the device is executing code from external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to exter- nal data memory. ea /v pp : external access enable. ea must be strapped to v ss in order to enable the 87c51/bh to fetch code from external program memory locations starting at 0000h up to ffffh. note, however, that if either of the lock bits is programmed, the logic level at ea is internally latched during reset. ea must be strapped to v cc for internal program execution. this pin also receives the programming supply volt- age (v pp ) during eprom programming. xtal1 : input to the inverting oscillator amplifier. xtal2 : output from the inverting oscillator amplifi- er. 272335 5 figure 3. using the on-chip oscillator oscillator characteristics xtal1 and xtal2 are the input and output, respec- tively, of an inverting amplifier which can be config- ured for use as an on-chip oscillator, as shown in figure 3. to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left uncon- nected, as shown in figure 4. there are no require- ments on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. an external oscillator may encounter as much as a 100 pf load at xtal1 when it starts up. this is due to interaction between the amplifier and its feedback capacitance. once the external signal meets the v il and v ih specifications the capacitance will not ex- ceed 20 pf. 272335 6 figure 4. external clock drive 5
87c51/80c51bh/80c31bh idle mode in idle mode, the cpu puts itself to sleep while all the on-chip peripherals remain active. the mode is invoked by software. the content of the on-chip ram and all the special functions registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hard- ware reset. it should be noted that when idle is terminated by a hardware reset, the device normally resumes pro- gram execution, from where it left off, up to two ma- chine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle is terminat- ed by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. power down mode to save even more power, a power down mode can be invoked by software. in this mode, the oscillator is stopped and the instruction that invoked power down is the last instruction executed. the on-chip ram and special function registers retain their val- ues until the power down mode is transmitted. on the 87c51/bh either a hardware reset or an ex- ternal interrupt can cause an exit from power down. reset redefines all the sfr's but does not change the on-chip ram. an external interrupt allows both the sfrs and on-chip ram to retain their values. to properly terminate power down, the reset or ex- ternal interrupt should not be executed before v cc is restored to its normal operating level, and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms). with an external interrupt int0 and int1 must be enabled and configured as level-sensitive. holding the pin low restarts the oscillator but bringing the pin back high completes the exit. once the interrupt is serviced, the next instruction to be executed after ret1 will be the one following the instruction that put the device into power down. design considerations exposure to light when the device is in operation may cause logic errors. for this reason, it is sug- gested that an opaque label be placed over the window when the die is exposed to ambient light. the 87c51/bh now have some additional fea- tures. the features are: asynchronous port reset, 4 interrupt priority levels, power off flag, ale dis- able, serial port automatic address recognition, serial port framing error detection, 64-byte en- cryption array, and 3 program lock bits. these features cannot be used with the older versions of 80c51bh/80c31bh. the newer version of 80c51bh/80c31bh will have change identifier " a'' appended to the lot number. table 2. status of the external pins during idle and power down mode program ale psen port0 port1 port2 port3 memory idle internal 1 1 data data data data idle external 1 1 float data address data power down internal 0 0 data data data data power down external 0 0 float data data data 6
87c51/80c51bh/80c31bh onc e mode th e onc e (``on-circui t emulation'' ) mod e facilitates testin g an d debuggin g o f system s usin g the 87c51/b h withou t th e 87c51/b h havin g t o b e re- move d fro m th e circuit . th e onc e mod e i s invoked by: 1 . pul l al e lo w whil e th e devic e i s i n rese t and psen i s high; 2 . hol d al e lo w a s rs t i s deactivated. whil e th e devic e i s i n onc e mode , th e por t 0 pins float , an d th e othe r por t pin s an d al e an d psen are weakl y pulle d high . th e oscillato r circui t remain s ac- tive . whil e th e 87c51/b h i s i n thi s mode , a n emula- to r o r tes t cp u ca n b e use d t o driv e th e circuit . nor- ma l operatio n i s restore d whe n a norma l rese t i s ap- plied. 87c51/bh express th e inte l expres s syste m offer s enhancement s to th e operationa l specification s o f th e mcs-5 1 family o f microcontrollers . thes e expres s product s are designe d t o mee t th e need s o f thos e applications whos e operatin g requirement s excee d commercial temperature. th e expres s progra m include s th e commercial standar d temperatur e rang e wit h burn-i n an d a n ex- tende d temperatur e rang e wit h o r withou t burn-in. wit h th e commercia l standar d temperatur e range, operationa l characteristic s ar e guarantee d ove r the temperatur e rang e o f 0 c to 70 c. with the extend- e d temperatur e rang e option , operationa l character- istic s ar e guarantee d ove r th e rang e of -4 0 c to + 85 c. th e optiona l burn-i n i s dynami c fo r a minimu m time o f 16 0 hour s a t 125 c with v cc = 6.9v 0.25v, followin g guideline s i n mil-std-883 , metho d 1015. packag e type s an d expres s version s ar e identified b y a one - o r two-lette r prefi x t o th e par t number . the prefixe s ar e liste d i n tabl e 3. fo r th e extende d temperatur e rang e option , this dat a shee t specifie s th e parameter s whic h deviate fro m thei r commercia l temperatur e rang e limits. tabl e 3 . prefi x identification prefix packag e temperature burn-in typ e range p plasti c commercia l no d cerdi p commercia l no n plc c commercia l no s qf p commercia l no t p plasti c extende d no t d cerdi p extende d no t n plc c extende d no t s qf p extende d no l p plasti c extende d yes l d cerdi p extende d yes l n plc c extende d yes note: contac t distributo r o r loca l sale s offic e t o matc h express prefi x t o prope r device. examples: p87c5 1 indicate s 87c5 1 i n a plasti c packag e and specifie d fo r commercia l temperatur e range , without burn-in. ld87c5 1 indicate s 87c5 1 i n a cerdi p packag e and specifie d fo r extende d temperatur e rang e wit h burn- in. 7
87c51 /80c51bh/80c31bh absolute maximum ratings : ambien t temperatur e unde r bia s .... - 4 0 c t o + 85 c storag e temperatur e ..................... - 65 c t o + 150 c voltag e o n ea /v pp pi n t o v ss .............. 0 v to + 13.0v voltag e o n an y othe r pi n t o v ss ........ - 0.5 v to + 6.5v maximu m i ol pe r i/ o pi n ...................................1 5 ma powe r dissipatio n ................................................1 .5w (base d o n packag e hea t transfe r limitations , no t de- vic e powe r consumption.) notice : thi s dat a shee t contain s preliminar y infor- matio n o n ne w product s i n production . i t i s vali d for th e device s indicate d i n th e revisio n history . the specification s ar e subjec t t o chang e withou t notice. * warning : stressin g th e devic e beyon d th e ``absolute maximu m ratings' ' ma y caus e permanen t damage. thes e ar e stres s rating s only . operatio n beyon d the ``operatin g conditions' ' i s no t recommende d an d ex- tende d exposur e beyon d th e ``operatin g conditions'' ma y affec t devic e reliability. operating conditions symbol description min max unit t a ambien t temperatur e unde r bias commercial 0 + 70 c express - 40 + 85 c v cc suppl y voltage 4 . 5 5.5 v f osc oscillato r frequency mhz 87c51/bh 3 . 5 12 87c51-1/bh-1 3 . 5 16 87c51-2/bh-2 0 . 5 12 87c51-24/bh-24 3 . 5 24 d c characteristics (over operating conditions) al l paramete r value s appl y t o al l device s unles s otherwis e indicated. symbol parameter min typ (1) max unit test conditions v il inpu t lo w voltage commercial - 0.5 0. 2 v cc - 0. 1 v express - 0.5 0. 2 v cc - 0.1 5 v v il1 inpu t lo w voltag e ea commercial 0 0. 2 v cc - 0. 3 v express - 0.5 0. 2 v cc - 0.3 5 v v ih inpu t hig h voltage (excep t xtal1 , rst) commercia l 0. 2 v cc + 0.9 v cc + 0. 5 v express 0. 2 v cc + 1 v cc + 0. 5 v v ih1 inpu t hig h voltage (xtal1 , rst) commercial 0. 7 v cc v cc + 0. 5 v express 0. 7 v cc + 0.1 v cc + 0. 5 v v ol outpu t lo w voltage (6) 0. 3 v i ol = 100 m a (2) (port s 1 , 2 , 3) 0.4 5 v i ol = 1. 6 ma (2) 1. 0 v i ol = 3. 5 ma (2) 8
87c51/80c51bh/80c31bh dc characteristics (over operating conditions) (continued) symbol parameter min typ (1) max unit test conditions v ol1 output low voltage (6) 0.3 v i ol e 200 m a (2) (port 0, ale, psen ) 0.45 v i ol e 3.2 ma (2) 1.0 v i ol e 7.0 ma (2) v oh output high voltage v cc b 0.3 v i oh eb 10 m a (3) (ports 1, 2, 3, ale, psen ) v cc b 0.7 v i oh eb 30 m a (3) v cc b 1.5 v i oh eb 60 m a (3) v oh1 output high voltage v cc b 0.3 v i oh eb 200 m a (3) (port 0 in external bus mode) v cc b 0.7 v i oh eb 3.2 ma (3) v cc b 1.5 v i oh eb 7.0 ma (3) i il logical 0 input current v in e 0.45v (ports 1, 2, 3) commercial b 50 m a express b 75 m a i li input leakage current g 10 m a 0.45 k v in k v cc (port 0) i tl logical 1-to-0 transition current v in e 2v (ports 1, 2, 3) commercial b 650 m a express b 750 m a rrst rst pulldown resistor 40 225 k x c io pin capacitance 10 pf 1 mhz, 25 c i cc power supply current (note 4) active mode 12 mhz (figure 5) 11.5 20 ma 16 mhz 26 ma 24 mhz 38 ma idle mode 12 mhz (figure 5) 3.5 7.5 ma 16 mhz 9.5 ma 24 mhz 13.5 ma power down mode 5 50 m a 9
87c51/80c51bh/80c31bh notes: 1. ``typicals'' are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. the values listed are at room temp, 5v. 2. capacitive loading on ports 0 and 2 may cause noise pulses above 0.4v to be superimposed on the v ol s of ale and ports 1, 2 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from 1 to 0. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8v. it may be desirable to qualify ale or other signals with a schmitt trigger, or cmos-level input logic. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9v cc specifi- cation when the address bits are stabilizing. 4. see figures 6 through 8 for i cc test conditions. minimum v cc for power down is 2v. 5. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port - port 0: 26 ma ports 1, 2, and 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink greater than the listed test conditions. 272335 26 figure 5. 87c51/bh i cc vs frequency 10
87c51/80c51bh/80c31bh 272335 10 figure 6. i cc test condition, active mode. all other pins are disconnected. 272335 8 figure 7. i cc test condition, idle mode. all other pins are disconnected. 272335 9 figure 9. i cc test condition, power down mode. all other pins are disconnected. v cc e 2v to 5.5v. 272335 11 figure 8. clock signal waveform for i cc tests in active and idle modes tclch e tchcl e 5ns 11
87c51/80c51bh/80c31bh explanation of the ac symbols each timing symbol has 5 characters. the first char- acter is always a `t' (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. a:address. c:clock. d:input data. h:logic level high. i:instruction (program memory contents). l:logic level low, or ale. p:psen . q:output data. r:rd signal. t:time. v:valid. w:wr signal. x:no longer a valid logic level. z:float. for example, tavll e time from address valid to ale low. tllpl e time from ale low to psen low. ac characteristics : (over operating conditions; load capacitance for port 0, ale, and psen e 100 pf; load capacitance for all other outputs e 80 pf) external memory characteristics all parameter values apply to all devices unless otherwise indicated. in this table, 87c51/bh refers to 87c51/bh, 87c51-1/bh-1 and 87c51-2/bh-2. symbol parameter oscillator units 12 mhz 24 mhz variable min max min max min max 1/tclcl oscillator frequency 87c51/bh 3.5 12 mhz 87c51-1/bh-1 3.5 16 mhz 87c51-2/bh-2 0.5 12 mhz 87c51-24/bh-24 3.5 24 mhz tlhll ale pulse width 127 43 2tclcl b 40 ns tavll address valid to ale low 87c51/bh 43 tclcl b 40 ns 87c51-24/bh-24 12 tclcl b 30 ns tllax address hold after ale low 53 12 tclcl b 30 ns tlliv ale low to valid instr in 87c51/bh 234 4tclcl b 100 ns 87c51-24/bh-24 91 4tclcl b 75 ns tllpl ale low to psen low 53 12 tclcl b 30 ns tplph psen pulse width 205 80 3tclcl b 45 ns tpliv psen low to valid instr in 87c51/bh 145 3tclcl b 105 ns 87c51-24/bh-24 35 3tclcl b 90 ns 12
87c51/80c51bh/80c31bh external memory characteristics all parameter values apply to all devices unless otherwise indicated. in this table, 87c51/bh refers to 87c51/bh, 87c51-1/bh-1 and 87c51-2/bh-2. (continued) symbol parameter oscillator units 12 mhz 24 mhz variable min max min max min max tpxix input instr hold after psen 00 0 n s tpxiz input instr float after psen 87c51/bh 59 tclcl b 25 ns 87c51-24/bh-24 21 tclcl b 20 ns taviv address to valid instr in 312 103 5tclcl b 105 ns tplaz psen low to address float 10 10 10 ns trlrh rd pulse width 400 150 6tclcl b 100 ns twlwh wr pulse width 400 150 6tclcl b 100 ns trldv rd low to valid data in 87c51/bh 252 5tclcl b 165 ns 87c51-24/bh-24 113 5tclcl b 95 ns trhdx data hold after rd 00 0 n s trhdz data float after rd 107 23 2tclcl b 60 ns tlldv ale low to valid data in 87c51/bh 517 8tclcl b 150 ns 87c51-24/bh-24 243 8tclcl b 90 ns tavdv address to valid data in 87c51/bh 585 9tclcl b 165 ns 87c51-24/bh-24 285 9tclcl b 90 ns tllwl ale low to rd or wr low 200 300 75 175 3tclcl b 50 3tclcl a 50 ns tavwl address to rd or wr low 87c51/bh 203 4tclcl b 130 ns 87c51-24/bh-24 77 4tclcl b 90 ns tqvwx data valid to wr transition 87c51/bh 33 tclcl b 50 ns 80c51-24/bh-24 12 tclcl b 30 ns 13
87c51/80c51bh/80c31bh external memory characteristics all parameter values apply to all devices unless otherwise indicated. in this table, 87c51/bh refers to 87c51/bh, 87c51-1/bh-1 and 87c51-2/bh-2. (continued) symbol parameter oscillator units 12 mhz 24 mhz variable min max min max min max twhqx data hold after wr 87c51/bh 33 tclcl b 50 ns 87c51-24/bh-24 7 tclcl b 35 ns tqvwh data valid to wr high 87c51/bh 433 7tclcl b 150 ns 87c51-24/bh-24 222 7tclcl b 70 ns trlaz rd low to address float 0 0 0 ns twhlh rd or wr high to ale high 87c51/bh 43 123 tclcl b 40 tclcl a 40 ns 87c51-24/bh-24 12 71 tclcl b 30 tclcl a 30 ns external program memory read cycle 272335 12 external data memory read cycle 272335 13 14
87c51/80c51bh/80c31bh external data memory write cycle 272335-14 external clock drive all parameter values apply to all devices unless otherwise indicated. in this table, 87c51/bh refers to 87c51/bh, 87c51-1/bh-1 and 87c51-2/bh-2. symbol parameter min max units 1/tclcl oscillator frequency 87c51/bh 3.5 12 mhz 87c51-1/bh-1 3.5 16 mhz 87c51-2/bh-2 0.5 12 mhz 87c51-24/bh-24 3.5 24 mhz tchcx high time 87c51/bh 20 ns 8751-24/bh-24 0.35tclcl 0.65tclcl ns tclcx low time 87c51/bh 20 ns 87c51-24/bh-24 0.35tclcl 0.65tclcl ns tclch rise time 87c51/bh 20 ns 87c51-24/bh-24 10 ns tchcl fall time 87c51/bh 20 ns 87c51-24/bh-24 10 ns external clock drive waveform 272335 15 15
87c51/80c51bh/80c31bh serial port timing - shift register mode 12 mhz 24 mhz variable oscillator symbol parameter oscillator oscillator units min max min max min max txlxl serial port clock 1.0 0.500 12tclcl m s cycle time tqvxh output data setup 700 284 10tclcl b 133 ns to clock rising edge txhqx output data hold ns after clock rising edge 87c51/bh 50 2tclcl b 117 87c51-24/bh-24 34 2tclcl b 34 txhdx input data hold 0 0 0 ns after clock rising edge txhdv clock rising edge 700 283 10tclcl b 133 ns to input data valid shift register mode timing waveforms 272335 18 ac testing input, output waveforms 272335 19 ac inputs during testing are driven at v cc b 0.5 for a logic ``1'' and 0.45v for a logic ``0.'' timing measurements are made at v ih min for a logic ``1'' and v il max for a logic ``0''. float waveforms 272335 20 for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh e g 20 ma. 16
87c51/80c51bh/80c31bh programming the 87c51 the part must be running with a 4 mhz to 6 mhz oscillator. the address of an eprom location to be programmed is applied to address lines while the code byte to be programmed in that location is ap- plied to data lines. control and program signals must be held at the levels indicated in table 4. normally ea /v pp is held at logic high until just before ale/prog is to be pulsed. the ea /v pp is raised to v pp , ale/prog is pulsed low and then ea /v pp is returned to a high (also refer to timing diagrams). note: exceeding the v pp maximum for any amount of time could damage the device permanently. the v pp source must be well regulated and free of glitches. definition of terms address lines : p1.0p1.7, p2.0p2.5, p3.4 re- spectively for a0 a14. data lines : p0.0p0.7 for d0d7. control signals : rst, psen , p2.6, p2.7, p3.3, p3.6, p3.7. program signals : ale/prog ,ea /v pp . table 4. eprom programming modes mode rst psen ale/ ea / p2.6 p2.7 p3.3 p3.6 p3.7 prog v pp program code data h l ? 12.75v l hhhh verify code data h l h h l l l h h program encryption h l ? 12.75v l h h l h array address 0 3f program lock bits bit 1 h l ? 12.75v hhhhh bit 2 h l ? 12.75v h h h l l bit 3 h l ? 12.75v h l h h l read signature byte h l h h lllll 272335 21 see table 4 for proper input on these pins figure 10. programming the eprom 17
87c51/80c51bh/80c31bh 272335 22 for compatibility, 25 pulses may be used. figure 11. programming waveforms programming algorithm refer to table 4 and figures 10 and 11 for address, data, and control signals set up. to program the 87c51 the following sequence must be exercised. 1. input the valid address on the address lines. 2. input the appropriate data byte on the data lines. 3. activate the correct combination of control sig- nals. 4. raise ea /v pp from v cc to 12.75v g 0.25v. 5. pulse ale/prog 5 times for the eprom array, and 25 times for the encryption table and the lock bits. repeat 1 through 5 changing the address and data for the entire array or until the end of the object file is reached. program verify verification may be done after programming either one byte or a block of bytes. in either case a com- plete verify of the array will ensure reliable program- ming of the 87c51. the lock bits cannot be directly verified. verification of the lock bits is done by observing that their fea- tures are enabled. rom and eprom lock system the program lock system, when programmed, pro- tects the onboard program against software piracy. the 80c51bh has a one level program lock system and a 64-byte encryption table. if program protection is desired, the user submits the encryption table with their code and both the lock bit and encryption array are programmed by the factory. the encryption array is not available without the lock bit. for the lock bit to be programmed, the user must submit an encryp- tion table. the 87c51 has a 3-level program lock system and a 64-byte encryption array. since this is an eprom device, all locations are user-program- mable. see table 5. encryption array within the eprom array are 64 bytes of encryption array that are initially unprogrammed (all 1's). every time that a byte is addressed during a verify, 6 ad- dress lines are used to select a byte of the encryp- tion array. this byte is then exclusive-nor'ed (xnor) with the code byte, creating an encryption verify byte. the algorithm, with the array in the un- programmed state (all 1's), will return the code in its original, unmodified form. for programming the en- cryption array, refer to table 4 (programming the eprom). when using the encryption array, one important fac- tor needs to be considered. lf a code byte has the value 0ffh, verifying the byte will produce the en- cryption byte value. lf a large block ( l 64 bytes) of code is left unprogrammed, a verification routine will display the contents of the encryption array. for this reason all unused code bytes should be pro- grammed with some value other than 0ffh, and not all of them the same value. this will ensure maxi- mum program protection. 18
87c51/80c51bh/80c31bh program lock bits the 87c51 has 3 programmable lock bits that when programmed according to table 5 will provide differ- ent levels of protection for the on-chip code and data. erasing the eprom also erases the encryption ar- ray and the program lock bits, returning the part to full functionality. reading the signature bytes the 87c51 and 80c51bh have 3 signature bytes in locations 30h, 31h, and 60h. to read these bytes follow the procedure for eprom verify, but activate the control lines provided in table 4 for read signa- ture byte. location device contents 30h all 89h 31h all 58h 60h 87c51 51h 80c51bh 11h erasure characteristics (windowed devices only) erasure of the eprom begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an ex- tended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadver- tent erasure. if an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. the recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrat- ed dose of at least 15 w-sec/cm 2 . exposing the eprom to an ultraviolet lamp of 12,000 m w/cm 2 rating for 30 minutes, at a distance of about 1 inch, should be sufficient. erasure leaves the array in an all 1's state. table 5. program lock bits and the features program lock bits protection type lb1 lb2 lb3 1 u u u no program lock features enabled. (code verify will still be encrypted by the encryption array if programmed.) 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the eprom is disabled. 3 p p u same as 2, also verify is disabled. 4 p p p same as 3, also external execution is disabled. 19
87c51/80c51bh/80c31bh eprom programming, eprom and rom verification characteristics: (t a e 21 cto27 c, v cc e 5v g 10%, v ss e 0v) symbol parameter min max units v pp programming supply voltage 12.5 13.0 v i pp programming supply current 75 ma 1/tclcl oscillator frequency 4 6 mhz tavgl address setup to prog low 48tclcl tghax address hold after prog 48tclcl tdvgl data setup to prog low 48tclcl tghdx data hold after prog 48tclcl tehsh p2.7 (enable ) high to v pp 48tclcl tshgl v pp setup to prog low 10 m s tghsl v pp hold after prog 10 m s tglgh prog width 90 110 m s tavqv address to data valid 48tclcl telqv enable low to data valid 48tclcl tehqz data float after enable 0 48tclcl tghgl prog high to prog low 10 m s eprom programming, eprom and rom verification waveforms 272335 23 * for programming conditions see figure 10. ** 5 pulses for the eprom array, 25 pulses for the encryption table and lock bits. 20

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